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To make an emulator, reproduce a target machine’s observable behavior in software: its CPU, memory map, devices, timing, inputs, outputs, and storage. Start with a small, documented target such as CHIP-8, build an interpreter and test it instruction by instruction, then add video, audio, interrupts, persistence, and performance only after the core is demonstrably correct.
Choose what “emulator” means
Before writing code, define the machine and the behavior you intend to reproduce. These projects differ substantially:
- CPU or instruction-set emulator: executes programs written for another processor.
- Console or arcade emulator: models a CPU plus memory, video, audio, controllers, cartridge hardware, and timing.
- Full-system emulator: models a complete computer with CPUs, memory, buses, and devices. QEMU describes system emulation this way, while also offering user-mode emulation for programs built for another architecture (QEMU emulation overview; QEMU system emulation).
- Compatibility layer, simulator, virtual machine, or dynamic translator: related approaches with different goals. Virtualization normally runs a compatible guest using hardware support; emulation reproduces a different machine in software.
Your first project should normally be a small virtual machine, educational CPU, or simple arcade platform—not a PlayStation, Nintendo 64, modern console, or PC.
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| Target | Why it is suitable | What you will learn |
|---|---|---|
| CHIP-8 | Small instruction set, simple display, timers, and 16-key input. A current guide describes the original system as having 35 instructions; extensions vary. | State modeling, decoding, memory, input, framebuffer output, and basic timing. |
| Intel 8080 or a small arcade board | A documented 8-bit CPU with a limited surrounding machine. | Flags, stack behavior, interrupts, memory mapping, and arcade video/input. |
| Game Boy, NES, Atari 2600, or Sega Master System | Approachable compared with later consoles, but no longer a one-weekend CPU exercise. | Banking, scanline timing, DMA, controller protocols, audio, and hardware quirks. |
| SNES, Mega Drive, PlayStation, Nintendo 64, PC, or modern console | Multiple processors, complex graphics and audio, undocumented behavior, and demanding timing. | Large-scale hardware modeling, reverse engineering, profiling, and compatibility engineering. |
CHIP-8 is a common beginner choice, not an objective universal “easiest” system. Its scope and instruction count depend on whether you implement the original specification or later variants (CHIP-8 guide).
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Decide what accuracy means
“Accurate” can refer to different properties:
- Instruction accuracy: registers, flags, memory accesses, and branches match the target.
- Functional compatibility: software produces the expected results.
- Timing or cycle accuracy: events occur on the target’s clock schedule.
- Pixel and audio accuracy: rendering, priority, samples, and mixing match the hardware.
- Bus accuracy and determinism: contention, side effects, and repeated runs are predictable.
Begin with functional correctness. Add cycle, pixel, audio, or bus detail when the target or compatibility tests require it. A JIT can improve throughput later, but an interpreter is easier to inspect and is usually sufficient for a small system.
What the emulator must reproduce
A useful mental model is:
ROM or program image
↓
memory bus and address map
↓
CPU fetch → decode → execute
↓
timers, interrupts, video, audio, input
↓
host display, sound, controls, and files
A console emulator is therefore more than an opcode switch. Depending on the target, it must model:
- CPU registers, flags, program counter, stack, reset state, and halt state;
- RAM, ROM, memory-mapped registers, mirroring, banking, and open-bus behavior;
- timers, interrupts, DMA, buses, and device ownership;
- video memory, rendering modes, palettes, sprites, priorities, and scanline events;
- controller ports, audio registers, mixing, and buffering;
- cartridges, firmware, boot ROMs, save RAM, disk images, or other storage;
- debugging, tracing, test fixtures, and deterministic replay.
Design the core before the frontend
Keep the emulated machine explicit and testable without a window or controller:
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A CPU state structure commonly contains registers, the program counter, stack pointer, flags, interrupt state, halted state, and a cycle counter. Peripheral state belongs in its own modules. A host library such as SDL, GLFW, winit, or an equivalent API is optional; it should translate host events and present output rather than leak host concepts into CPU code.
Read the specification first
Collect documentation for one hardware revision and record:
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- register names and widths, reset values, and instruction encodings;
- instruction effects, flags, cycle counts, illegal-opcode behavior, and stack rules;
- the complete address map, including mirrors and device registers;
- boot sequence, interrupt vectors and priority, timer frequencies, and DMA rules;
- video dimensions, modes, access restrictions, and timing;
- controller layout, audio behavior, cartridge formats, firmware requirements, and save hardware;
- regional revisions and known undocumented behavior.
For real hardware, distinguish official documentation, reverse-engineered notes, test-ROM results, physical observations, and conventions copied from existing emulators. A widely repeated implementation is not automatically proof.
Implement memory and loading
Start with a byte-addressable representation and two explicit operations:
read(address) → byte write(address, value)
Use bounds checks while developing. Route ranges to ROM, RAM, video RAM, registers, timers, controller ports, mappers, or expansion hardware as the specification requires. Test 8-bit and multi-byte accesses independently; verify endianness, alignment, mirroring, read-only and write-only registers, and side effects.
The loader should open a file, validate its size and header, identify its format, map it into the address space, retain useful metadata, and reject unsupported images clearly. A cartridge may include separate ROM, RAM, a bank controller, battery-backed saves, and metadata. Some software also requires a boot ROM or firmware; a ROM file is not necessarily the whole machine.
Build the fetch–decode–execute interpreter
The basic loop is target-specific, but the structure is familiar:
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while running:
if interrupt_is_serviceable():
cycles = service_interrupt()
elif cpu_is_halted():
cycles = halt_step()
else:
opcode = fetch()
instruction = decode(opcode)
cycles = execute(instruction)
advance_devices(cycles)
Each instruction should define its operands, destination, flags, program-counter and stack effects, memory accesses, cycle count, and behavior for unsupported opcodes. Do not silently convert unknown instructions to no-ops unless the target specifies that behavior. During development, report the opcode, program counter, registers, and recent memory accesses when execution fails.
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function step_cpu():
opcode = bus.read8(cpu.pc)
cpu.pc = cpu.pc + 1
switch opcode:
case LOAD_IMMEDIATE:
value = bus.read8(cpu.pc)
cpu.pc = cpu.pc + 1
cpu.a = value
return LOAD_IMMEDIATE_CYCLES
case ADD:
cpu.a = add_with_flags(cpu.a, cpu.b)
return ADD_CYCLES
case JUMP:
target = bus.read16(cpu.pc)
cpu.pc = target
return JUMP_CYCLES
default:
raise UnsupportedOpcode(opcode)
Be exact about arithmetic and flags
Common defects include carry versus borrow, half-carry, signed overflow, rotate-through-carry, multi-byte zero flags, and flags that must remain unchanged. Write isolated tests for arithmetic helpers before relying on them in games. Intermediate arithmetic may use a wider host type, but the final result and each flag must follow the target CPU’s rules; no single formula applies to every architecture.
Add shared timing, interrupts, and DMA
Do not run CPU, timer, video, and audio as unrelated host loops. Advance them from a shared emulated clock or a defined event schedule. Instruction-count scheduling is easy to test; a master clock is better for tightly coupled systems; host sleeping only regulates presentation and cannot reproduce scanline or bus timing.
Implement interrupt requests and enables, priority, vector addresses, entry and return timing, nested behavior, timer overflow and reload, DMA bus ownership, CPU stalls, and access restrictions. The exact ordering is hardware-specific. A functional first pass can defer sub-cycle details, but real console compatibility often depends on them.
Keep graphics, input, and audio separate
Graphics
Start with a framebuffer and a host presentation routine, or dump frames to images for tests. Keep emulated video behavior separate from how the host window displays it. Console video may require tile and sprite decoding, palettes, scrolling, priority rules, sprite limits, scanline timing, video interrupts, and mid-frame register changes. A picture that looks plausible can still be wrong if timing or priority is wrong.
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Input
Translate keyboard or gamepad events into target button bits, matrix lines, or controller registers:
host keyboard/gamepad
↓
target input state and registers
Do not place host key names in CPU instructions. A reusable libretro core can use the framework’s controller abstraction and callbacks (Libretro input API).
Audio
Model the target’s channel state, frequency, volume, and register behavior, then mix into a buffered host queue and resample when necessary. Audio may be disabled in the first visible milestone, but programs can still depend on audio-register side effects.
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Unit and instruction tests
- Arithmetic, shifts, rotates, flags, stack operations, and address calculations.
- Memory reads and writes, decoding, serialization, and reset behavior.
- For every instruction: initial state, final state, program counter, memory changes, and cycle count.
Integration and reference tests
- ROM loading, banking, interrupts, timers, DMA, video modes, controllers, and saves.
- Publicly redistributable test programs where their licenses permit use.
- Short programs compared with a trusted emulator or physical hardware at instruction, scanline, frame, or event boundaries.
Deterministic debugging
Given the same image and inputs, produce the same result. Add a trace line containing the program counter, opcode, registers, flags, stack pointer, and cycle count. A command-line test that emits serial or memory output is often more diagnostic than a blank game window. Save-state snapshots and deterministic replay make regressions reproducible.
QEMU’s system-emulation documentation also treats testing and tooling as part of emulator engineering, not as an afterthought (QEMU system-emulation documentation).
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A practical milestone plan
- Command-line core: define state, memory, reset, loading, a few instructions, tracing, and unit tests.
- Complete CPU: implement documented instructions, flags, stack, branches, invalid-opcode handling, and cycle accounting.
- Timers and interrupts: add vectors, requests, halt behavior, and a shared clock.
- Display: add a framebuffer, target renderer, window or frame dumps, and a frame limiter.
- Input and audio: map controllers, model audio registers, and add host buffering.
- Platform hardware: add boot ROMs, mappers, save RAM, special chips, and documented quirks only as required.
- Optimization and distribution: profile first, then consider dispatch optimizations, lookup tables, JIT translation, save states, configuration, packaging, or frontend integration.
Interpreter, JIT, and frontend trade-offs
Interpreter versus JIT
An interpreter is the best starting point for learning, correctness, diagnostics, and small 8-bit systems. Dynamic translation becomes useful when a mature project is too slow, but introduces translated-code invalidation, self-modifying code, precise exceptions, interrupt boundaries, permissions, and more difficult debugging. Faster execution is not evidence of better emulation.
Standalone application versus reusable core
A standalone program has fewer lifecycle and API constraints. A libretro core can share controller, video, audio, serialization, and frontend integration across multiple frontends, but must follow those contracts (Libretro core development). In either design, keep the machine core testable without a window or audio device.
Diagnose the failures that waste the most time
- Wrong initial state: execute the boot ROM or document a post-boot shortcut instead of guessing register values.
- Endianness errors: test every multi-byte read and write;
12 34is not universally0x1234. - Program-counter errors: check operand fetch order, signed branch offsets, conditional-cycle counts, and interrupt return addresses.
- Flag errors: test half-carry, borrow, overflow, rotate, and unchanged-flag cases.
- Flat-memory assumptions: replace a permanent byte array with mapped devices when banking, mirroring, DMA, or register side effects appear.
- Unsynchronized devices: drive CPU, timers, video, audio, and DMA from one emulated time base.
- Host throttling: sleeping to reach a frame rate does not make scanlines or interrupts accurate.
- Testing only graphics: use traces, serial output, memory dumps, and test ROMs to isolate CPU and bus defects.
- Undocumented behavior: label unsupported cases rather than silently guessing and claiming full accuracy.
How difficult is a real console emulator?
A small virtual machine is approachable for a programmer comfortable with binary notation, bitwise operations, data structures, file I/O, and debugging. A simple 8-bit console is a substantial project because graphics timing, interrupts, mappers, audio, and controllers matter. A 16- or 32-bit console is advanced; a modern console or full PC is a major engineering effort involving multiple processors, complex devices, reverse engineering, and extensive compatibility testing.
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Use ROMs, firmware, BIOS files, and test programs that you are legally entitled to use. An emulator can be open source while the software or firmware it runs remains proprietary. Trademarks, documentation, reverse-engineering rules, and interoperability exceptions vary by jurisdiction, so avoid treating a project’s legality as automatic merely because you wrote the code. Homebrew and public test programs are safer development material.
Quick Recap
First-project checklist
- Choose one target, hardware revision, accuracy goal, and legal software source.
- Collect a specification and write the state structure and memory map.
- Implement reset, memory reads and writes, and a validated loader.
- Implement instruction fetch, decode, execution, flags, stack behavior, and tests.
- Add cycle accounting, timers, interrupts, and DMA according to the target.
- Add a minimal framebuffer, then input, then audio.
- Compare deterministic traces with test programs, a reference implementation, or hardware.
- Add a debugger, save states, and replay before optimizing.
- Profile compatibility failures and implement platform-specific hardware only when evidence requires it.
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