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Ben C.’s open-source v2f project converts Verilog circuit designs into blueprint strings for Factorio 2.0. Its most striking documented example is an RV32IM RISC-V processor built from in-game combinators, with sample programs—including a “hello_world” example—running in Factorio. This is a software compiler and circuit-building demonstration, not a physical CPU or a claim of independently verified processor performance.
What v2f does
v2f lets Factorio players describe combinator circuits in Verilog, a hardware-description language, then turns those designs into blueprint strings that can be imported into the game. The project’s stated goal, as software engineer Ben C. put it to Hackster, is: “Input Verilog, output pure vanilla Factorio Blueprints.” The project repository also offers Rust and Lua APIs for authoring designs.
The important distinction is that v2f compiles a design into an in-game arrangement of combinators and wires. The result is not a physical electronic circuit, and the documented CPU example should be understood as a processor implemented inside Factorio’s circuit network.
How the Verilog becomes a blueprint
The documented flow uses Yosys for synthesis and mapping before v2f turns the mapped design into a Factorio layout. The repository describes Yosys scripts for the RTL and mapping stages, followed by v2f processing that outputs JSON blueprint strings. In Hackster’s account of Ben’s explanation, a front end creates a logic graph, and a Rust stage reads a Yosys-derived MappedDesign before arranging combinators and wires.
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That last step matters: a logical circuit description still needs a physical layout that fits Factorio’s grid and power system. Ben told Hackster that the routing logic places power poles to cover combinators and uses a graph-traversal heuristic to reduce copper wires while maintaining one power-distribution network. He said the RISC-V core needed a couple of manually placed substations for full coverage. This is the developer’s explanation of the layout approach, not a published routing benchmark.
The RISC-V example: what it demonstrates
The repository documents an RV32IM processor in examples/riscv_v2f_optimized/top_v2f. It identifies Ultraembedded’s design as the starting point and says the author modified multiplication and division to produce a more efficient design for synthesis. The example uses a cross-compiler targeting freestanding RV32IM, and the README describes sample programs running in Factorio, including hello_world after the processor is compiled and its clock is started.
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That is meaningful evidence of a substantial in-game combinator build: the project documents a processor design and programs executing in the game. It does not establish instruction-set conformance testing, clock rate, execution speed, benchmark results, or a performance comparison with other Factorio circuits or physical processors. The README also notes a bug in the displayed ASCII font and says the image had not yet been rerun, so that visual should not be treated as a polished or verified output capture.
Ways to explore the project
The repository documents several routes, but they serve different purposes. Its browser-based backend GUI can place combinators and simulate them; the README explicitly says it is not the complete Verilog-to-blueprint flow because running Yosys in a browser is difficult. The full project also documents a hosted development container, a Docker/VS Code setup, and bare-metal dependency installation. The author recommends the Lua flow for beginners.
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- Try the browser backend: use it to explore combinator placement and simulation, not as a complete browser-based Yosys compilation workflow.
- Use the documented development setup: the repository describes a hosted container, Docker with VS Code, and bare-metal dependency installation for working with the fuller toolchain.
- Start with Lua if you are new to the project: this is the README’s recommendation for beginners.
Setup instructions and compatibility can change, so check the current repository documentation before choosing a route. The project is listed under the AGPL-3.0 license.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What makes v2f notable—and what remains unproven
For Factorio players, v2f offers a way to express complex combinator designs in Verilog rather than constructing every connection manually, then generate a blueprint layout. The documented toolset also includes simulation and SVG rendering, alongside its authoring APIs. The RV32IM example shows the scale of design the project presents, but the available documentation does not compare v2f’s speed, correctness rate, or ease of use against manual construction or other circuit compilers.
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The FOSSi Foundation’s newsletter, published April 14, 2026, also describes the project and quotes Ben on its compiler flow and routing. That account is corroboration of the project description, not independent reproduction of the CPU build.
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