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Newly reported die-shot images and a teardown account describe Huawei’s Kirin 9050 Pro as two vertically bonded silicon layers: one focused on compute and another carrying SRAM/cache and other supporting blocks. The reports attribute N+3 and N+2 process assignments to the respective layers, but Huawei and SMIC have not confirmed those node claims. The reported 120.65 mm² measurement is for a die layer—not a verified measurement of the complete stacked package.
What the die shots and teardown report
Wccftech reported on October 2, 2026, that Kurnal Insights had published die-shot images identified as HiSilicon Hi36E0, also known as Kirin 9050. Its account describes compute and SRAM/cache functions on vertically bonded dies. A separate Notebookcheck report, published October 3 and based on Geekerwan’s teardown, describes copper-to-copper hybrid bonding between the layers.
In that teardown interpretation, the secondary layer carries cache, I/O interfaces and PLLs, while major functional blocks span both dies. Notebookcheck also reports roughly 80,000 through-silicon vias (TSVs), which carry power and signals between layers, and estimates that TSV keep-out zones use about 8% of the bottom die’s usable area. These are figures and architectural interpretations reported from the teardown, not a public Huawei or SMIC specification.
How small is the reported footprint?
Wccftech gives each die as 11.13 mm × 10.84 mm, or 120.65 mm², and compares that figure with a reported 122 mm² footprint for the Kirin 9030S. These are reported measurements, not independently verified metrology. The comparison concerns the stated die-layer area; it does not establish that the complete two-layer package occupies 120.65 mm² or that the new chip is smaller than every earlier Kirin design.
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Stacking changes how functions are arranged in three dimensions. It does not make either silicon layer’s physical dimensions smaller by itself. A smaller individual die can be relevant to manufacturing, but these reported dimensions alone do not show that Kirin 9050 Pro has better production yield. Stacking may also introduce additional assembly and package-yield considerations, and the reports do not establish a yield result.
Are the reported N+3 and N+2 nodes confirmed?
No. Wccftech attributes the claim that the compute layer uses SMIC’s N+3 process and the SRAM layer uses N+2 to a tipster. Notebookcheck repeats that split while explicitly noting Huawei and SMIC have not directly confirmed either assignment. Huawei’s announcement describes the architecture but does not assign a process node to each layer. The N+3/N+2 split should therefore be treated as an attributed report, not an official specification.
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What Huawei means by LogicFolding
Huawei announced on September 9, 2026, that Kirin 9050 Pro would debut in the Mate XT 2, and presented LogicFolding as its commercial chip architecture. Huawei describes it as vertically integrating selected chip areas using hybrid bonding: areas that might otherwise be connected across a die can be placed on vertically connected levels, shortening some paths. The company says typical compute-block wire lengths are reduced by around 20%, with critical paths reduced by up to 70%; those are Huawei’s claims.
The teardown description and Huawei’s explanation are consistent with a design that uses vertical connections, but the reported stack should not be mistaken for a complete official layer-by-layer specification. Notebookcheck compares the cache arrangement to AMD’s 3D V-Cache in the limited sense that separate bonded silicon is involved. Its account says major blocks are distributed across both layers, so this is not evidence that the two architectures are the same.
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Huawei’s performance and density claims
Huawei says Kirin 9050 Pro reaches 238 million transistors per square millimeter, compared with around 155 million/mm² previously, which the company characterizes as a 55% increase. Huawei also reports a 70 TOPS NPU, 141% higher than its stated predecessor comparison; 42% higher GPU performance; and an 18% CPU benchmark improvement. These are vendor-reported figures, not independent measurements in the teardown accounts.
At equal performance, Huawei says energy use is lower by 66% for the NPU, 58% for the GPU and 41% for the CPU performance core. The announcement does not make those claims an independently measured, apples-to-apples comparison across devices or workloads. The reports available here do not provide independent comparative measurements of performance, power, yield or total package footprint.
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