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AcqRel’s Factorio Yosys Project Put a RISC-V Core in Factorio

Hackster.io reported that AcqRel connected Yosys to Factorio combinators to demonstrate a 32-bit RISC-V soft core. A separate project, v2f, documents a related Verilog-to-blueprint workflow, but no link between the projects is established.
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AcqRel’s reported Factorio Yosys project connected the Yosys hardware-synthesis tool to Factorio’s in-game combinators, turning a RISC-V design into a circuit that runs inside the game. Hackster.io described it as a “fully-functional” 32-bit RISC-V soft-core demonstration, but that wording is not evidence of formal RISC-V certification, physical CPU performance, or independent testing.

How the reported AcqRel project worked

Yosys is an open synthesis suite used to translate hardware-description-language designs into circuit representations. Hackster.io reported that AcqRel’s backend mapped an HDL project into Factorio combinator circuits, including a 32-bit RISC-V soft-core processor. The article also mentioned a working Snake game as another example. Hackster.io’s report traces the project to a Mastodon post by Frans Skarman, who credited a friend as its creator; the available account does not independently establish that person’s identity beyond the AcqRel handle used in the coverage.

This is a software-generated circuit demonstration inside a game, not a physical RISC-V chip. “Fully-functional” should be read as the report’s description of the demonstration, not as a conformance claim or a measured comparison with conventional processors.

What the reported speed means

Hackster.io attributed a speed of 1.82 Hz to Frans Skarman, with Factorio capped at 60 frames per second. Skarman said that uncapping the game’s frame rate could make the processor run faster. The captured report does not establish a reliable publication year, and the figure is not an independently verified current benchmark; it applies to the reported demonstration and its game-rate conditions, not to v2f or RISC-V processors generally.

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How v2f relates—and how it does not

A separate project, Ben C.’s v2f, documents a related Verilog-to-Factorio workflow. Its repository describes conversion of Verilog designs into Factorio 2.0 blueprint output, with Rust and Lua APIs. The project provides an RV32IM example based on an Ultraembedded core, sample programs, and a cross-compiler for freestanding RV32IM. Ben C. says the example’s hello-world program runs after the core is compiled and clocked. These details come from the v2f repository and the author’s project post.

The v2f material helps explain the general idea: Yosys produces a design representation, then a Rust backend maps it to combinators, places and routes the circuit, and emits a blueprint. The project also includes a Rust combinator simulator for comparing behavior with Verilog simulation, Lua scripting, a node-based GUI, and SVG rendering. Its browser demo covers backend placement and simulation rather than the entire Yosys compilation flow.

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There is no established connection between v2f and AcqRel’s project, and the two should not be treated as the same implementation or as a predecessor and successor. Their reported timing figures are not directly comparable.

What the two projects document

Project Documented workflow and example Timing evidence License evidence
AcqRel’s reported Factorio Yosys project Hackster.io reports a Yosys-to-Factorio combinator backend and a 32-bit RISC-V soft-core demonstration; the article also mentions Snake. Hackster.io attributes 1.82 Hz at a 60-fps cap to Frans Skarman. The report’s publication year is not established in the captured page, and the figure is not independently verified. Hackster.io said the license was unspecified at the time of its article.
Ben C.’s v2f Repository documents Verilog-to-Factorio 2.0 blueprint output and an RV32IM example, alongside Rust and Lua APIs. The author reports a 41-game-tick minimum clock period for the v2f RISC-V example. This is an author-reported timing-analysis result, not a wall-clock benchmark. The v2f repository identifies its license as AGPL-3.0.

The v2f author also describes partitioned placement, simulated annealing, routing, and power coverage; for the RISC-V layout, he says a couple of substations required manual placement. This is evidence about v2f, not about AcqRel’s implementation.

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Ways to explore the idea

Factorio is the environment for the in-game circuit demonstration. The v2f repository and its browser simulator are separate ways to inspect related project material; the browser demo does not perform the full Yosys compilation flow. The repository is open source under its stated license, while the older AcqRel coverage did not specify a license.

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